The present invention relates to electronic device design, and particularly to the layout of vias for electronic circuits.
Electronic devices, particularly integrated circuits, comprise a large number of components fabricated by layering several different materials onto a silicon wafer. In order for the components to function as an electronic device, they are selectively, electrically connected to one another. Metal lines are utilized to electrically connect components. The metal lines provide electrical connection within a layer, while vias connect different metallization and via layers. It is important that a good connection between the via and metal line exists in order to ensure that the proper amount of current is carried with minimal resistance between the connected components.
When designing an electronic device, a designer creates a circuit description, including electrical connection of the components. The circuit description is input into a computer aided design (CAD) software package to form a three-dimensional geometric image of the electronic device, known as a layout. Software vending companies such as Cadence, Mentor Graphics, and Integrated Silicon Systems provide CAD software specially designed for electronic device design and manufacture.
Typically, a CAD system for designing electronic devices contains several components to assist with circuit design, for example: a schematic editor, a logic compiler, a logic simulator, a logic verifier, and a layout program. The schematic editor allows designers to create and/or modify a schematic diagram, i.e., circuit description, using the computer""s display and input devices, and generates a net list, i.e., a summary of connections between components, in the process. The logic compiler receives the net list as input, and utilizing a component database, writes the necessary information for layout, verification, and simulation into a schematic object file having a format specifically optimized for layout, verification, and simulation. The logic verifier checks the schematic diagram for design errors, such as multiple outputs connected together, overloaded signal paths, etc., and generates error indications if any such design problems exist. The logic simulator uses the schematic object file and simulation models created by the designer, and generates a set of simulation results, based upon instructions, initial conditions, and input signal values provided either in the form of a file or as user input.
The layout program generates geometric data from which a semiconductor chip, circuit board, integrated circuit, or other electronic device is laid out and produced. Generally, a layout comprises a set of geometric shapes contained in several layers. In a layout, metal lines are represented as trenches in a layer, and vias are represented as holes in a layer. Typically, the layout is checked to ensure that it meets all of the design requirements, e.g., that there are a sufficient number of vias between a particular upper metal line and a lower metal line to carry the requisite current between the metal lines. The result is a set of design files that describes the layout. The design files are then converted into pattern generator files used to produce patterns by an optical or electron beam pattern generator that are called masks. Masks are then utilized to print the layout onto a wafer using photolithography techniques.
Current CAD programs for designing electronic devices automate the process of generating an electronic device layout, but do not address many problems related to electronic device layouts. A difficult problem relating to via spacing and arrangement arises as electronic device sizes continue to shrink. In the past, an electronic device layout was large enough to accommodate vias with a sufficient size that the vias would fill properly, i.e., without voids and other defects in the metal filling the via hole, when the electronic device was manufactured. Today, with electronic device designs, and individual electronic device components such as vias, becoming increasingly smaller and smaller, reliable filling of vias during manufacture is no longer assured. Partially filled vias result in less current connecting electronic device components, leading to underpowered components and slower operation of the electronic device. Partially filled vias also increase the resistance to electrical flow, leading to overheating problems and possible burnout of an electronic device.
Along with decreased sizes of components, shrunk electronic device designs also require individual components to be spaced closer together than ever before. For vias, close spacing raises the possibility of bridging between vias during manufacture of the electronic device. When bridging or partial bridging occurs between vias that are on the same node, i.e., carry electric current between the same metal lines, excess defect generation during inspection results. Excess defect generation increases the amount of time spent performing inspection of an electronic device, thus increasing the cost of producing the device.
There is a need for modifying dense via arrays in electronic device design layouts in order to prevent filling problems for the vias within dense via arrays. There is also a need for modifying dense via arrays in order to reduce defect generation issues during inspection of electronic devices.
These needs and others are met by embodiments of the present invention, which provide a method and apparatus for identifying particular via arrays in an electronic device layout where the vias in an array are on the same node. Based upon the combined area of the vias within a via array on the same node, the present invention replaces the vias in the via array with a lesser number of vias, each of which is larger than the original vias, such that the total area of the vias is unchanged, or is greater. Embodiments of the present invention use aerial image simulations of the printed resist patterns to calculate the total area of the vias in the original via array, and also use aerial image simulations of the printed resist patterns to calculate the total area of the via area after the original vias have been replaced with larger vias. The final results on a wafer are larger vias that print and fill without issues, and have sufficient spacing so as to prevent bridging.
Accordingly, one aspect of the invention relates to a method for resizing vias in an electronic device design. The method identifies vias that each contact a pair of metal lines, then determines the combined area of the identified vias. At least one polygon is created wherein the area of the at least one polygon is at least as large as the combined area of the identified vias. The identified vias are replaced with at least a via that is defined by the at least one polygon.
In certain embodiments, aerial image simulations are utilized to determine the combined area of the identified vias, as well as the area of the vias defined by the at least one polygon.
Another aspect of the present invention relates to a computer system comprising a processor, a display connected to the processor, an input device connected to the processor, and a cursor control device connected to the processor. The processor carries out instructions for creating a design layout for an electronic device. The processor further carries out instructions for resizing vias in the design of an electronic device. Resizing vias is carried out by identifying vias that each contact a pair of metal lines, and determining the combined area of the identified vias. At least one polygon is created wherein the area of the at least one polygon is the same as the combined area of the identified vias. The identified vias in the design are replaced with at least a via that is defined by the at least one polygon.
Another aspect of the present invention relates to a computer readable medium bearing instructions for processing a computer-generated electronic device layout. The instructions contained on the computer readable medium, when executed, are arranged to cause a computer system to identify vias that each contact a pair of metal lines, and determine the combined area of the identified vias. The instructions create at least one polygon having at least as large a combined area as the combined area of the identified vias, and replace the identified vias with at least a via defined by the at least one polygon.
Replacing a via array composed of small vias that connect two metal lines with a via array composed of larger vias connecting the same two metal lines greatly improves the electronic device manufactured from the electronic device layout without substantially increasing the design time or cost of manufacturing the electronic device. This is accomplished by creating via arrays where the individual vias are spaced far enough apart to prevent bridging concerns during manufacture, are large enough that they will completely fill, with copper or other conductive metal for example, and are more easily printed because of their larger size.
Additional advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the invention may be realized and attained by the instrumentalities and combinations, particularly pointed out in the appended claims.